/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved.
 * Description   : RoCE MPU cmd
 * Author        : /
 * Create        : /
 * Notes         : /
 * History       : /
 */

#ifndef ROCE_MPU_CMD_H
#define ROCE_MPU_CMD_H

#include "vroce_context_format.h"

/*
 * Commands between RoCE driver to MPU
 */
enum {
    /* FUNC CFG */
    ROCE_MPU_CMD_SET_FUNC_STATE = 0, /**< Set roce_vld in function table @see > roce_set_func_state_cmd_s */
    ROCE_MPU_CMD_SET_CPU_ENDIAN, /**< Set cpu endian in function table @see > roce_set_cpu_endian_cmd_s */
    ROCE_MPU_CMD_GET_CFG_INFO, /**< Get roce-related configuration from cfg_data @see > roce_get_cfg_info_cmd_s */
    ROCE_MPU_CMD_DEL_FUNC_RES, /**< Clear relevant resources when FLR @see > roce_set_func_state_cmd_s */
    ROCE_MPU_CMD_GET_FUNC_TABLE, /**< Get function table @see > roce_get_func_table_cmd_s */
    ROCE_MPU_CMD_ADD_MAC = 10, /**< Add MAC to MAC table @see > roce_cfg_mac_cmd_s */
    ROCE_MPU_CMD_DEL_MAC, /**< Delete MAC from MAC table @see > roce_cfg_mac_cmd_s */
    ROCE_MPU_CMD_ADD_IPSU_MAC, /**< Add entry to IPSURX VF table MAC mode @see > roce_cfg_ipsu_mac_cmd_s */
    ROCE_MPU_CMD_DEL_IPSU_MAC, /**< Delete entry from IPSURX VF table MAC mode @see > roce_cfg_ipsu_mac_cmd_s */
    ROCE_MPU_CMD_GET_MAC_VNI,

    /* BOND */
    ROCE_MPU_CMD_BOND_SET_STATE = 20,
    ROCE_MPU_CMD_BOND_GET_ER_FWD_ID,
    ROCE_MPU_CMD_BOND_SET_ER_FWD_ID,
    ROCE_MPU_CMD_BOND_ER_FWD_ID_COMBINE,
    ROCE_MPU_CMD_BOND_ER_FWD_ID_COMPACT,
    ROCE_MPU_CMD_GET_GROUP_ID,

    /* CC */
    ROCE_MPU_CMD_CC_CFG_CCF_PARAM = 40, /**< Config CCF param table @see > roce_cc_cfg_param_cmd_s */
    ROCE_MPU_CMD_CC_CFG_DCQCN_PARAM, /**< Config DCQCN param table @see > roce_cc_cfg_param_cmd_s */
    ROCE_MPU_CMD_CC_CFG_IPQCN_PARAM, /**< Config IPQCN param table @see > roce_cc_cfg_param_cmd_s */
    ROCE_MPU_CMD_CC_CFG_LDCP_PARAM, /**< Config LDCP param table @see > roce_cc_cfg_param_cmd_s */
    ROCE_MPU_CMD_CC_SET_BW_CTRL,
    ROCE_MPU_CMD_CC_QUERY_BW_CTRL,

    /* DFX */
    ROCE_MPU_CMD_DFX_CACHE_OUT = 55, /**< Cache out a type of chip resource @see > roce_dfx_cache_out_cmd_s */
    ROCE_MPU_CMD_DFX_SET_CAP_CFG, /**< Set capture configuration table @see > roce_dfx_cfg_cap_param_cmd_s */
    ROCE_MPU_CMD_DFX_GET_CAP_CFG, /**< Get capture configuration table @see > roce_dfx_cfg_cap_param_cmd_s */
    ROCE_MPU_CMD_DFX_READ_CAP_CTR, /**< Read capture num counter @see > roce_dfx_cap_ctr_cmd_s */
    ROCE_MPU_CMD_DFX_CLEAR_CAP_CTR, /**< Read and clear capture num counter @see > roce_dfx_cap_ctr_cmd_s */

    /* ULP */
    ROCE_MPU_CMD_ULP_AA_SET_DD_CFG = 128,
    ROCE_MPU_CMD_ULP_AA_CTRL_READY,
    ROCE_MPU_CMD_ULP_AA_SWITCH_IO,
    ROCE_MPU_CMD_ULP_AA_FAKE_DATA,
    ROCE_MPU_CMD_ULP_AA_CLAER_ACT_CTRL_BMP,

    ROCE_MPU_CMD_MAX = 256
};

enum vroce_up_ops {
    VROCE_MPU_CMD_VF_ADD,
    VROCE_MPU_CMD_VF_SHOW,
    VROCE_MPU_CMD_VF_DEL,
    VROCE_MPU_CMD_VF_LIST,
    VROCE_MPU_CMD_VF_SET,
    VROCE_MPU_CMD_DSCP_ADD,
    VROCE_MPU_CMD_DSCP_DEL,
    VROCE_MPU_CMD_DSCP_SET,
    VROCE_MPU_CMD_DSCP_FLOW_CTRL,
    VROCE_MPU_CMD_GLOBAL_SET,
    VROCE_MPU_CMD_VF_STATS_SHOW,
    VROCE_MPU_CMD_VF_GLOBAL_SHOW,

    VROCE_MPU_CMD_PROBE_FILTER,
    VROCE_MPU_CMD_PROBE_STOP,
    VROCE_MPU_CMD_DFX_SET_CAP_CFG,
    VROCE_MPU_CMD_DFX_GET_CAP_CFG,
    VROCE_MPU_CMD_DFX_CLEAR_CAP_COUNTER,
    VROCE_MPU_CMD_DFX_READ_CAP_COUNTER,
    VROCE_MPU_CMD_ICQ_THRESHOLD_SET,
    VROCE_MPU_CMD_ICQ_THRESHOLD_SHOW,
    VROCE_MPU_CMD_ADD_SLAVE_FEATURE,
    VROCE_MPU_CMD_SHOW_FEATURE,
    VROCE_MPU_CMD_UPDATE_FLEXQ_CFG,
    VROCE_MPU_CMD_CLEAR_FLEXQ_CFG,

    /* MIG */
    VROCE_MPU_CMD_MIG_SAVE_CC,
    VROCE_MPU_CMD_MIG_RESTORE_CC,
    VROCE_MPU_CMD_MIG_SET_FLOW_HUNG_FLAG,
    VROCE_MPU_CMD_MIG_GET_CACHE_LINE,

    VROCE_MPU_CMD_MAX
};

#endif /* ROCE_MPU_CMD_H */

